TWO-DIMENSIONAL PMOS DEVICES FOR PROVIDING CMOS IN BACK-END LAYERS OF INTEGRATED CIRCUIT DEVICES
In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a sourc...
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Main Authors | , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
21.12.2023
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Subjects | |
Online Access | Get full text |
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Summary: | In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC). |
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Bibliography: | Application Number: US202217842462 |