SEMICONDUCTOR DEVICE PRE-CLEANING

A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a...

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Main Authors CHANG, Chih-Wei, CHEN, Hung-Hsu, WENG, Ting-Wei, HSU, Peng-Hao, CHAO, Yi-Hsiang, TSAI, Ming-Hsing, CHOU, Chih-Sheng, YANG, Shu-Ting, HSU, Hung-Chang, HUANG, Chun-Hsien
Format Patent
LanguageEnglish
Published 30.11.2023
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Summary:A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.
Bibliography:Application Number: US202217804447