SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES

Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal w...

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Bibliographic Details
Main Authors Lee, Jang Woo, Rajendra, Srinivas, Pai, Anil, Ramachandra, Venkatesh Prasad
Format Patent
LanguageEnglish
Published 30.11.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
Bibliography:Application Number: US202217828708