MEMORY CELL ARRAY UNIT

A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one...

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Bibliographic Details
Main Authors KANDA, YASUO, SAKAI, LUI
Format Patent
LanguageEnglish
Published 23.11.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.
Bibliography:Application Number: US202118248541