STACKED MEMORY POP STRUCTURE AND PACKAGING METHOD THEREOF

A stacked memory POP structure and method are disclosed. The POP structure includes a first package unit of three-dimensional memory chip package and a system-in-package (SiP) package unit of two-dimensional fan-out peripheral circuit. The first package unit includes: memory chips laminated in a ste...

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Bibliographic Details
Main Authors Chen, Yenheng, Lin, Chengchung
Format Patent
LanguageEnglish
Published 02.11.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A stacked memory POP structure and method are disclosed. The POP structure includes a first package unit of three-dimensional memory chip package and a system-in-package (SiP) package unit of two-dimensional fan-out peripheral circuit. The first package unit includes: memory chips laminated in a stepped configuration; wire bonding structures; and a first encapsulating layer. The SiP package unit includes: a first rewiring layer; a peripheral circuit chip a second rewiring layer bonded to the peripheral circuit chip; metal connection pillars electrically connected with the first rewiring layer and the second rewiring layer; a second encapsulating layer, which encapsulates the peripheral circuit chip and the metal connection pillars; and metal bumps on the first rewiring layer. The wire bonding structures are wire-bonded to the second rewiring layer to connect the memory chips to the second rewiring layer, thereby achieving attachment between the first package unit and the SiP package unit.
Bibliography:Application Number: US202318139777