METHOD OF TESTING STRUCTURES AND STACKING WAFERS

Disclosed herein are integrated circuit (IC) structures and methods for fabricating and testing such IC structures prior to dicing from a semiconductor wafer on which the IC structures are formed. In one example, a method for fabricating an IC structure includes contacting a first plurality of test...

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Bibliographic Details
Main Authors WANG, Yan, LIN, Hui-Wen, CHEN, I-Ru, CHONG, Nui
Format Patent
LanguageEnglish
Published 05.10.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:Disclosed herein are integrated circuit (IC) structures and methods for fabricating and testing such IC structures prior to dicing from a semiconductor wafer on which the IC structures are formed. In one example, a method for fabricating an IC structure includes contacting a first plurality of test pads of the IC structure with one or more test probes. The first plurality of test pads are disposed within or on a first dielectric layer within a scribe lane, i.e., a test region. A first metal layer is formed over the first plurality of test pads if a predefined test criteria is met as determined using information obtained through first plurality of test pads using the one or more test probes. The first metal layer is a layer formed in a die region of an IC die that is being fabricated in the wafer.
Bibliography:Application Number: US202217712052