TWO-STAGE CACHE PARTITIONING

Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides addit...

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Bibliographic Details
Main Authors Van Doren, Stephen, Abraham, Philip, Herdrich, Andrew, Gupta, Ritu
Format Patent
LanguageEnglish
Published 05.10.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address-which is provided in a memory access request, and which indicates a location in one virtual cache-to another address which indicates another location in a different virtual cache.
Bibliography:Application Number: US202217711471