METHOD OF DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of designing a layout of a semiconductor device includes forming a second layout by analyzing a first layout and correcting at least a portion of a plurality of filler cells, wherein the forming the second layout includes detecting transition regions due to a difference in width by respecti...

Full description

Saved in:
Bibliographic Details
Main Authors Park, Juyun, NA, Yeojin, Kim, Jongdoo
Format Patent
LanguageEnglish
Published 14.09.2023
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method of designing a layout of a semiconductor device includes forming a second layout by analyzing a first layout and correcting at least a portion of a plurality of filler cells, wherein the forming the second layout includes detecting transition regions due to a difference in width by respectively comparing a first width of a first active line and a second width of a second active line with a width of a dummy active line, in the first layout; and correcting the dummy active line of the first filler cell by analyzing the detected transition regions, wherein, in the correcting the dummy active line of the first filler cell, the dummy active line is corrected to be a corrected dummy active line having the same width as an active line having a narrower width, among the first and second active lines.
Bibliography:Application Number: US202218061789