SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A trench capacitor having an inner electrode and a node dielectric layer is formed in a trench of the substrate. The inner electrode and the node dielectric layer extend...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
07.09.2023
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A trench capacitor having an inner electrode and a node dielectric layer is formed in a trench of the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the trench capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug. |
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Bibliography: | Application Number: US202217683382 |