LAYOUT OF CONDUCTIVE VIAS FOR SEMICONDUCTOR DEVICE

Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the periphera...

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Bibliographic Details
Main Author Shibata, Kayoko
Format Patent
LanguageEnglish
Published 10.08.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the peripheral region. The one or more wirings are disposed adjacent to the memory array region. One or more power vias of the plurality of power vias are disposed through a wiring of the one or more wirings.
Bibliography:Application Number: US202217665367