Two-Level Arbitration in a Reconfigurable Processor

A coarse-grained reconfigurable (CGR) processor includes agents coupled to a first network, an array of CGR units connected by a second network, and a tile agent coupled between the first and second networks. The tile agent includes links to receive requests for transactions on the first network, re...

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Bibliographic Details
Main Authors SHAH, Manish K, BAXLEY, John Philipp
Format Patent
LanguageEnglish
Published 10.08.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A coarse-grained reconfigurable (CGR) processor includes agents coupled to a first network, an array of CGR units connected by a second network, and a tile agent coupled between the first and second networks. The tile agent includes links to receive requests for transactions on the first network, request queues respectively associated with the links, credit counters associated with respective agents, a first arbiter, and a second arbiter. The first arbiter selects a request from the received requests for transactions and enters the selected request into a request queue associated with a link that received the selected request. The second arbiter chooses a request from an oldest entry of each request queue based on the credit counters, sends a transaction based on the chosen request over the first network, and removes the chosen request from its respective request queue.
Bibliography:Application Number: US202318107690