LOW RESISTANCE METAL TO SEMICONDUCTOR CONTACTS FOR INTEGRATED NMOS AND PMOS TRANSISTORS

Complementary metal-oxide-semiconductor (CMOS) devices and methods related to selective metal contacts to n-type and p-type source and drain semiconductors are discussed. A p-type metal is deposited on n- and p-type source/drains. The p-type metal is selectively removed from the n-type source/drains...

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Bibliographic Details
Main Authors Metz, Matthew V, Jezewski, Christopher J
Format Patent
LanguageEnglish
Published 22.06.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Complementary metal-oxide-semiconductor (CMOS) devices and methods related to selective metal contacts to n-type and p-type source and drain semiconductors are discussed. A p-type metal is deposited on n- and p-type source/drains. The p-type metal is selectively removed from the n-type source/drains but remains on dielectric materials adjacent the n-type source/drains. An n-type metal is deposited on the n-type source/drains while the remaining p-type metal seals the dielectric materials to protect the n-type metal from contamination. The n-type metal is then sealed using another p-type metal. A contact fill material contacts the resultant source and drain contact stacks.
Bibliography:Application Number: US202117559332