MEMORY CELL OF CHARGE-TRAPPING NON-VOLATILE MEMORY

A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first do...

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Bibliographic Details
Main Authors SUN, Wein-Town, HSU, Chia-Jung
Format Patent
LanguageEnglish
Published 22.06.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.
Bibliography:Application Number: US202218079081