QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SERIALIZER/DESERIALIZER
A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the sec...
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Main Authors | , , , , , , , , |
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Format | Patent |
Language | English |
Published |
22.06.2023
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Subjects | |
Online Access | Get full text |
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Summary: | A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway. |
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Bibliography: | Application Number: US202117557166 |