PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT OF ANY PORTION OF A SUM

One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with...

Full description

Saved in:
Bibliographic Details
Main Authors Gradstein, Amit, Dutta, Mrinmay, Rubanovich, Simon, Sperber, Zeev
Format Patent
LanguageEnglish
Published 22.06.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.
Bibliography:Application Number: US202117559811