FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plura...

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Bibliographic Details
Main Authors Nikonov, Dmitri E, Sebot, Julien, Pasdast, Gerald S, Liff, Shawna M, Munoz, Robert J, Elsherbini, Adel A, Chandwani, Neelam, Karnik, Tanay, Bharath, Krishna, Molnar, Carleton L, Swan, Johanna M, Nassif, Nevine
Format Patent
LanguageEnglish
Published 15.06.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.
Bibliography:Application Number: US202117548304