IN-SITU LOW TEMPERATURE DIELECTRIC DEPOSITION AND SELECTIVE TRIM OF PHASE CHANGE MATERIALS

• Main Authors: MIYAZOE, HIROYUKI, Sagianis, Matthew Peter, Utomo, Henry K, Buzi, Luxherta
• Format: Patent
• Language: English
• Published: 08.06.2023
• Subjects: CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.