INTEGRATION MANUFACTURING METHOD OF DEPLETION HIGH VOLTAGE NMOS DEVICE AND DEPLETION LOW VOLTAGE NMOS DEVICE

An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high vol...

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Bibliographic Details
Main Authors Weng, Wu-Te, Hsiung, Chih-Wen, Yang, Ta-Yung
Format Patent
LanguageEnglish
Published 08.06.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.
Bibliography:Application Number: US202217981387