NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF

• Main Authors: Park, Jungmin, Kim, Minseok, Kim, Suyong, Park, Ilhan, Park, Junyong
• Format: Patent
• Language: English
• Published: 18.05.2023
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.