METHOD OF FABRICATING SUPER-JUNCTION BASED VERTICAL GALLIUM NITRIDE JFET AND MOSFET POWER DEVICES

• Main Authors: Drowley, Clifford, Cui, Hao
• Format: Patent
• Language: English
• Published: 27.04.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.