ACCELERATING TRIANGLE VISIBILITY TESTS FOR REAL-TIME RAY TRACING

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask...

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Bibliographic Details
Main Authors OLIVER, Levi, BURGESS, John, DELIGIANNIS, Johannes, ANDERSSON, Magnus, URALSKY, Yury, MORETON, Henry Packard, MUTHLER, Gregory
Format Patent
LanguageEnglish
Published 16.03.2023
Subjects
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.
Bibliography:Application Number: US202217946221