Semiconductor Structure with Recessed Top Semiconductor Layer in Substrate and Method of Fabricating the Same

• Main Authors: Liu, Ko-Cheng, Min, Wei-Lun, Liu, Chang-Miao
• Format: Patent
• Language: English
• Published: 02.03.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method includes providing a substrate including a first semiconductor layer over a dielectric layer, thinning the first semiconductor layer, forming a stack of alternating second semiconductor layers and third semiconductor layers over the thinned first semiconductor layer, forming a fin active region protruding from the substrate including a portion of the thinned first semiconductor layer and the stack of alternating second semiconductor layers and third semiconductor layers, forming isolation features over an exposed portion of the dielectric layer, forming a dummy gate stack over the fin active region, forming a source/drain (S/D) recess in the fin active region adjacent to the dummy gate stack, forming an epitaxial S/D feature in the S/D recess, removing the second semiconductor layers to form openings between the third semiconductor layers, and forming a metal gate stack in the openings and in place of the dummy gate stack.