MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting v...

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Bibliographic Details
Main Authors KIM, Hyeran, CHO, Sungyong
Format Patent
LanguageEnglish
Published 02.03.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.
Bibliography:Application Number: US202217692447