UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM

An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.

Saved in:
Bibliographic Details
Main Authors Zhu, Fangfang, Tai, Ying Y, Zhu, Jiangli
Format Patent
LanguageEnglish
Published 02.03.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.
Bibliography:Application Number: US202117463100