Semiconductor Package with Lead Tip Inspection Feature

A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of el...

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Bibliographic Details
Main Authors Chiang, Chau Fatt, Saw, Khay Chwan Andrew, Tan, Chee Voon
Format Patent
LanguageEnglish
Published 16.02.2023
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Summary:A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices each of the sidewall-facing terminals is electrically connected to the semiconductor die of the respective packaged semiconductor device. Each of the sidewall-facing terminals of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.
Bibliography:Application Number: US202217973864