THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CAPPED ISOLATION TRENCH FILL STRUCTURE AND METHODS OF MAKING THE SAME

A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically...

Full description

Saved in:
Bibliographic Details
Main Author OTSU, Yoshitaka
Format Patent
LanguageEnglish
Published 19.01.2023
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer, memory stack structures, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack, an isolation trench fill structure interposed between the alternating stack and the vertically alternating sequence and including a trench fill material portion and a capping dielectric structure overlying the trench fill material portion, and a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a top surface of one of the lower-level metal interconnect structures.
Bibliography:Application Number: US202117376490