METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electro...

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Bibliographic Details
Main Authors Tsui, Ying Kit Felix, Chen, Shih-Hsien, Lo, Wen-Shun, Wu, Tai-Yi
Format Patent
LanguageEnglish
Published 29.12.2022
Subjects
ELECTRICITY
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Summary:In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.
Bibliography:Application Number: US202117408621