SEMICONDUCTOR DIE WITH TAPERED SIDEWALL IN PACKAGE AND FABRICATING METHOD THEREOF

• Main Authors: LIN, Po-Yao, YEW, Ming-Chih, LAI, Po-Chen, WANG, Chin-Hua, YEH, Shu-Shen, LIN, Yu-Sheng, JENG, Shin-Puu
• Format: Patent
• Language: English
• Published: 22.12.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.