NON-VOLATILE MEMORY DIE WITH ON-CHIP DATA AUGMENTATION COMPONENTS FOR USE WITH MACHINE LEARNING

Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components...

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Bibliographic Details
Main Authors Navon, Ariel, Bazarsky, Alexander
Format Patent
LanguageEnglish
Published 22.12.2022
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Summary:Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.
Bibliography:Application Number: US202217897028