PACKAGING SUBSTRATE WITH LOW THERMAL RESISTANCE AND LOW PARASITIC INDUCTANCE

• Main Authors: SHI, Wei, ZHU, Lijun, HUANG, Hao, ZHU, Huanlin, CHEUNG, Siu Kwan
• Format: Patent
• Language: English
• Published: 01.12.2022
• Subjects: BASIC ELECTRIC ELEMENTS; DEVICES USING STIMULATED EMISSION; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.