METHOD OF SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS

A method includes disposing a first power rail, a second power rail and a third power rail arranged in order; disposing a first cell row having a first row height between the first power rail and the second power rail; and disposing a second cell row having the first row height between the third pow...

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Bibliographic Details
Main Authors LU, Lee-Chung, HOU, Yung-Chin, CHEN, Xiang-Dong, ZHUANG, Hui-Zhong, LIN, Tzu-Ying
Format Patent
LanguageEnglish
Published 01.12.2022
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A method includes disposing a first power rail, a second power rail and a third power rail arranged in order; disposing a first cell row having a first row height between the first power rail and the second power rail; and disposing a second cell row having the first row height between the third power rail and the second power rail. Each of the first power rail and the third power rail has a first width, and the second power rail has a second width larger than the first width.
Bibliography:Application Number: US202217884293