SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT

A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell...

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Bibliographic Details
Main Authors Fujiwara, Hidehiro, Wang, Yih, Chiu, Yi-Hsun
Format Patent
LanguageEnglish
Published 10.11.2022
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.
Bibliography:Application Number: US202217870208