SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

A semiconductor memory device includes a plurality of first chips and a second chip. The second chip is connected to the first chips via M second channels. Upon receipt of first data via the first channel at a transfer rate N times higher than the transfer rate per a single second channel, the secon...

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Bibliographic Details
Main Authors MATSUDERA, Katsuki, OOTOMO, Goichi
Format Patent
LanguageEnglish
Published 22.09.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A semiconductor memory device includes a plurality of first chips and a second chip. The second chip is connected to the first chips via M second channels. Upon receipt of first data via the first channel at a transfer rate N times higher than the transfer rate per a single second channel, the second chip transmits the first data to the N first chips in parallel via the N second channels by sorting the first data into N pieces in a unit of bus width of the first channel. Upon receipt of L pieces of third data in parallel from L of the M second channels, the second chip sequentially concatenates the L pieces of third data in a unit of bus width of the first channel and transmits the data via the first channel at the transfer rate L times higher the transfer rate per the single second channel.
Bibliography:Application Number: US202117470427