Seal Ring Designs Supporting Efficient Die to Die Routing

Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through...

Full description

Saved in:
Bibliographic Details
Main Authors Huang, Long, Dabral, Sanjay, Ni, Chi Nung, Jangam, SivaChandra
Format Patent
LanguageEnglish
Published 15.09.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.
Bibliography:Application Number: US202117460806