MULTILEVEL DRIVER FOR HIGH SPEED CHIP-TO-CHIP COMMUNICATIONS

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a commo...

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Bibliographic Details
Main Author Ulrich, Roger
Format Patent
LanguageEnglish
Published 07.07.2022
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PULSE TECHNIQUE
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.
Bibliography:Application Number: US202217700182