CACHE LINE INVALIDATION TECHNOLOGIES

Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more o...

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Bibliographic Details
Main Authors MCDONNELL, Niall D, RICHARDSON, Bruce, RAVISUNDAR, Subhiksha
Format Patent
LanguageEnglish
Published 07.07.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU).
Bibliography:Application Number: US202217707010