SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION

• Main Authors: CHEN, Shih-Shiung, FANG, Chun-Chieh, WEN, Chi-Yuan, WU, Jian, HUANG, Chien-Chang, WU, Ming-Chi, CHENG, Jung-Yu, HUANG, Wei-Tung, YEH, Yu-Lung
• Format: Patent
• Language: English
• Published: 23.06.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.