DIE-TO-WAFER BONDING STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may...

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Bibliographic Details
Main Authors Kang, Unbyoung, Hong, Jiseok, Park, Sangcheon, Kang, Myungsung, Lee, Hyuekjae, Hwang, Jihwan, Kim, Taehun
Format Patent
LanguageEnglish
Published 09.06.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
Bibliography:Application Number: US202217680477