Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry

• Main Authors: Nahar, Manuj, Fan, Darwin Franseda, Liao, Albert, Chavan, Ashonita A, Vasilyeva, Irina V, Hull, Jeffrey B, Lin, Xue-Feng, Antonov, Vassil N, Liu, Hung-Wei, Khandekar, Anish A, Laskar, Masihhur R
• Format: Patent
• Language: English
• Published: 19.05.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.