IDENTIFYING TEST COVERAGE GAPS FOR INTEGRATED CIRCUIT DESIGNS BASED ON NODE TESTABILITY AND PHYSICAL DESIGN DATA

Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on t...

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Bibliographic Details
Main Authors Narula, Kapil, Kalyan, Rahul, Liang, Hongkun, Jindal, Anurag
Format Patent
LanguageEnglish
Published 28.04.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.
Bibliography:Application Number: US202117450093