PROCESSOR WITH INSTRUCTION CONCATENATION

A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.

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Bibliographic Details
Main Authors Diewald, Horst, Zipperer, Johann
Format Patent
LanguageEnglish
Published 10.03.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.
Bibliography:Application Number: US202117528403