Hybrid On/Off-Chip Memory Architecture For Graph Analytics

The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operation...

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Bibliographic Details
Main Authors BERTACCO, Valeria, ADDISIE, Abraham
Format Patent
LanguageEnglish
Published 20.01.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.
Bibliography:Application Number: US202016932183