HALOGEN TREATMENT FOR NMOS CONTACT RESISTANCE IMPROVEMENT

Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region...

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Bibliographic Details
Main Authors CLENDENNING, Scott B, CHOUKSEY, Siddharth, LU, Mengcheng, KAVALIEROS, Jack T, HARATIPOUR, Nazila, DEWEY, Gilbert, METZ, Matthew V, JHA, Jitendra Kumar, MATTSON, Eric Charles
Format Patent
LanguageEnglish
Published 30.12.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.
Bibliography:Application Number: US202016913859