HALOGEN TREATMENT FOR NMOS CONTACT RESISTANCE IMPROVEMENT
Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region...
Saved in:
Main Authors | , , , , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
30.12.2021
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal. |
---|---|
Bibliography: | Application Number: US202016913859 |