METHODS AND APPARATUS FOR IMPROVED FAILURE MODE AND EFFECTS ANALYSIS

A processor generates a first allocation matrix and accesses a representation of relationships between individual system elements, representing lower-level system elements to be considered at a current-level of design of a product, with each other. The processor creates an element entry in the first...

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Bibliographic Details
Main Authors Kymal, Chandran, Gruska, Gregory Francis
Format Patent
LanguageEnglish
Published 30.12.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor generates a first allocation matrix and accesses a representation of relationships between individual system elements, representing lower-level system elements to be considered at a current-level of design of a product, with each other. The processor creates an element entry in the first allocation matrix for at least a subset of the individual system elements and creates an element entry in the first allocation matrix for one or more directional relationships between the individual system elements as indicated in the representation. The processor creates function and requirements entries in the first allocation matrix based on pre-existing requirements for the product applicable to the current-level of design and generates additional function and requirements, as well as creates corresponding entries in the first allocation matrix, based on current-level architectural requirements, including at least functions and requirements for one or more of the directional relationships indicated in the representation.
Bibliography:Application Number: US202016913759