CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW

• Main Authors: Tsair, Yong-Shiuan, Hsu, Yu-Ling, Shih, Hung-Ling, Li, Ping-Cheng, Liu, Po-Wei, Lin, Chia-Sheng, Huang, Wen-Tuo, Yang, Shih Kuang
• Format: Patent
• Language: English
• Published: 23.12.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.