LOGIC BASED READ SAMPLE OFFSET IN A MEMORY SUB-SYSTEM

The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset...

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Bibliographic Details
Main Authors Sheperek, Michael, Liikanen, Bruce A
Format Patent
LanguageEnglish
Published 09.12.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.
Bibliography:Application Number: US202117445395