Overlay Alignment Mark and Method for Measuring Overlay Error

An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a...

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Bibliographic Details
Main Authors Liu, Chengcheng, Huang, Shouyan, Han, Chunying, Ma, Weimin
Format Patent
LanguageEnglish
Published 09.12.2021
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a first pattern, which is a portion of the lower-layer pattern and comprises a pair of solid features formed in the first layer; and a second pattern, which is a portion of the upper-layer pattern and comprises two pairs of hollowed features formed in the second layer, with two imaginary lines connecting between geometric centers of respective pairs in the two pairs of hollowed features extending in two mutually orthogonal directions, respectively; an orthographic projection of the pair of solid features on the wafer at least partially overlaps with an orthographic projection of a respective pair of hollowed features on the wafer.
Bibliography:Application Number: US202117315619