OVERLAY ALIGNMENT MARK, METHOD FOR MEASURING OVERLAY ERROR, AND METHOD FOR OVERLAY ALIGNMENT

• Main Authors: Huang, Shouyan, LIU, Chengcheng, Han, Chunying, MA, Weimin
• Format: Patent
• Language: English
• Published: 09.12.2021
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CINEMATOGRAPHY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

An overlay alignment mark, a method for measuring overlay error, and a method for overlay alignment are provided in the embodiments of the present disclosure. the overlay alignment mark is formed on a wafer to be detected and comprises a first pattern and a second pattern, the first pattern being located in a first layer of the wafer and comprising two first solid sub-patterns which are provided opposite to each other in a first direction and extend in a second direction perpendicular to the first direction, respectively, and the second pattern being located in a second layer above the first layer of the wafer and comprising two first hollowed sub-patterns which are provided opposite to each other in the first direction and two to second hollowed sub-patterns which are provided opposite to each other in the second direction; and two opposite side edges of each of the two first solid sub-patterns extending in the second direction are at least partially exposed from a respective one of the two first hollowed sub-patterns.