INTEGRATED CIRCUIT STRUCTURE

An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the iso...

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Bibliographic Details
Main Authors LIANG, Chia-Ming, CHANG, Chi-Hsin, NG, Jin-Aun, MOR, Yi-Shien, CHIU, Huai-Hsien, LEE, Yi-Juei
Format Patent
LanguageEnglish
Published 28.10.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
Bibliography:Application Number: US202117366544