INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS

According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The...

Full description

Saved in:
Bibliographic Details
Main Authors TANG, Kin Wai, SEET, Chim Seng, YU, Bo, LIN, Benfu
Format Patent
LanguageEnglish
Published 16.09.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.
Bibliography:Application Number: US202016816365